Welcome to IEEE TCCA Email-Monthly, Nov. 2002: 1. ISCA-2003: The 30th Ann Int'l Symposium on Computer Architecture The ABSTACT DEADLINE for submissions is NOV. 11, 2002 at 6PM PST(US) submitted by: Yuanyan Zhou Call for Paper http://isca03.cs.princeton.edu/index.html 2. ERSA'03: The 2003 International Conference on ENGINEERING OF=20 RECONFIGURABLE SYSTEMS AND ALGORITHMS=20 submitted by: Toomas Plaks Call for Paper http://www.scism.sbu.ac.uk/ERA/ersa.html 3. ASAP 2003: 14th IEEE International Conference on Application-specific Systems, Architectures and Processors submitted by Mainak Sen Call For Papers http://www.ece.rice.edu/asap2003/=20 4. ICS '03: 17th International Conference on Supercomputing submitted by Michael Gschwind CALL FOR PAPERS http://www.csit.fsu.edu/ics03 5. SAN-2: 2nd Annual Workshop on Novel Uses of System Area Networks Call-for-papers http://www.csl.cornell.edu/SAN-2/ * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members,=20 send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20 ----------------------------------------------------------------------- Qing (Ken) Yang, Professor =09 Distinguished Engineering Professor e-mail: qyang@ele.uri.edu =20 Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 =20 University of Rhode Island Fax (401) 782-6422 =20 Kingston RI. 02881 http://www.ele.uri.edu/~qyang = =20 ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------- ISCA-2003 Call for Paper The 30th Annual International Symposium on Computer Architecture San Diego, California, USA June 9-11, 2003 http://isca03.cs.princeton.edu/index.html --------------------------------------------------------------------- The ABSTACT DEADLINE for submissions is NOVEMBER 11, 2002 at 6PM PST (US)= .=20 The PAPER DEADLINE for submissions is one week later, NOVEMBER 18, 2002 at 6PM PST (US). NO FURTHER EXTENSIONS WILL BE GRANTED. --------------------------------------------------------------------- ISCA has been a premier forum to present and discuss innovative ideas and quantified experience in the area of computer architecture. Architecture today is quite different from it has been in the past. Thus the 30th ISCA looks to focus on architecture in the broad sense, looking at architectures for specific application areas, and system architecture issues. While more conventional architecture papers will be considered, innovative architectures that address a specific application domain, or novel approaches to solve the problems of computing systems will be encouraged. =20 Topics include but not limited to:=20 - computer system architectures=20 - processor architectures=20 - power-efficient architectures=20 - multiprocessors and multicomputers=20 - memory hierarchy subsystems=20 - storage subsystem architectures=20 - network processor and router architectures=20 - application-specific, or embedded architectures=20 - architectures for secure computing=20 - architectural implications and application characteristics=20 - performance evaluation and measurement of real systems We particularly encourage submissions containing highly original ideas.=20 The submission process for ISCA 2003 will include two parts: an abstract and a paper submission. The abstract includes a description (100-300 words) of the paper and an indication of the key topics of the paper. The ABSTACT DEADLINE for submissions is NOVEMBER 11, 2002 at 6PM PST (US). The PAPER DEADLINE for submissions is one week later, NOVEMBER 18, 2002 at 6PM PST (US). NO FURTHER EXTENSIONS WILL BE GRANTED. Authors are required to submit both the abstract and paper electronically at Your paper should be formatted in PDF format for letter-size paper. Submissions must be viewable by Adobe Acrobat Reader (version 3.0 or higher). The submission should not exceed 7000 words or 10 pages of conference paper format using 10pt fonts. Submissions exceeding the required limit will not be reviewed by the program committee. Finally, it is requested that authors should not disclose their identity, as they will be reviewed blind. Submissions will be judged on originality, significance, interest, clarity, and correctness. ISCA requires that papers not be submitted simultaneously to any other conferences or publications, that submissions not be previously published, and that accepted papers not be subsequently published elsewhere. All submissions will be acknowledged by November 25, 2002. If your submission is not acknowledged by this date, please contact the program chair promptly at isca03pcchair@cs.princeton.edu . Workshops and Tutorials As in previous years, a series of tutorials and workshops will be held immediately preceding the symposium. Tutorial and workshop proposals will be accepted until December 20, 2002. If you wish to organize a workshop or tutorial (1/2 or 1 day), email a proposal to the Workshop/Tutorials Chair (Patricia Teller, pteller@cs.utep.edu ). For tutorials, the proposal must include title, brief description of topics to be covered, and bio of the speakers. If you wish to organize a workshop (1 or 2 days), the proposal must include title, brief description of topics to be covered, and bio of the organizers. For more information, see the ISCA 2003 web page. Yuanyuan Zhou ISCA-2003 Publicity Chair University of Illinois, Urbana Champaign yyzhou@cs.uiuc.edu -------------------------------------------------------------------------= - The 2003 International Conference on ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS --- ERSA'03 http://www.scism.sbu.ac.uk/ERA/ersa.html a part of The 2003 International MultiConference in Computer Science http://www.ashland.edu/~iajwa/conferences/ June 23--26, 2003=20 Monte Carlo Resort, Las Vegas, Nevada, USA Introduction The recent years have shown a continuous interest in using reconfigurable computing platform for the design of application-specific computer=20 systems. The advances in reconfigurable computing architecture, in algorithm implementation methods, and in automatic mapping methods of algorithms=20 into=20 hardware and processor spaces form together a new paradigm of computing=20 and programming that has often been called `Computing in Space and Time' or `Computing without Computer'. This conference focuses on the different approaches in engineering of reconfigurable systems and implementing of algorithms, including theory,=20 architecture, algorithms, design systems and applications that=20 demonstrate the benefits of reconfigurable computing. ** Keynote Talk The Rise of Reconfigurable Systems Dr. Nick Tredennick, Editor of Dynamic Silicon, Gilder Publishing, USA ** Invited Talks 1. Prof. Majid Sarrafzadeh, UCLA, USA =20 2. Prof. Juergen Becker, Univ. of Karlsruhe, Germany 3. ... ** Topics 1. Theory - Synthesis, Mapping, Parallelization, Partitioning ... 2. Software - CAD, Languages, Compilers, Operating Systems ...=20 3. Hardware - Dynamic Hardware, CSoCs, Reconfigurable Processors ...=20 4. Applications - Wireless Communication, Software Radio, Smart Cameras=20 ... ** Focus Sessions A number of Focus Sessions are planned to organize. The preliminary list = is given below. We accept proposals for new sessions. Please contact with ER= SA Chairman Toomas Plaks (ersa@sbu.ac.uk) ** Best Papers After the conference, authors of best papers will be invited to submit an extended version for publication in a Special Issue of an International Journal (last year was The Journal of Supercomputing, Kluwer). ** Desert Seminar After the conference (probably on June 26th), an one day social event `Desert Seminar' will be organized. The aim of this is to help to create=20 personal contacts between researchers and give more possibilities for discussions etc. It is planned to make a daytrip to the Death Valley. Interested persons should take contact with ERSA Chairman Toomas Plaks (ersa@sbu.ac.uk) and make their proposals. ** Exhibition An exhibition is planned for the duration of the MultiConferences. Interested parties should contact ERSA Chairman Toomas Plaks. All exhibitors will be considered to be the co-sponsors of the=20 conferences. ** Important Dates ** Full papers (10 pages, IEEE format): February 10, 2003=20 ** Notification of acceptance: March 24, 2003 ** Camera-ready papers and registration: April 21, 2003 ** Conference: June 23--26, 2003 ** Submission Prospective authors are invited to submit an original, unpublished work, not currently submitted for publication or for consideration elsewhere.=20 Full details will be available soon on the ERSA Web-site. ** Other Conferences of Interest Together with ERSA there will be other conferences of interest: *VLSI - International Conference on VLSI *CIC - International Conference on Communications in Computing *ICWN - International Conference on Wireless Networks *CISST - International Conference on Imaging Science, Systems and Technology *IC - International Conference on Internet Computing *PDPTA - International Conference on Parallel and Distributed Processing=20 Techniques and Applications For more details about other conferences, visit the Web-site: The 2003 International MultiConference in Computer Science http://www.ashland.edu/~iajwa/conferences/ For more details about ERSA, visit our Web-site:=20 http://www.scism.sbu.ac.uk/ERA/ersa.html. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ General Topics The topics of interest include, but are not limited to: 1. Theory, Mapping and Parallelization. o Theoretical models of computing in space-time and adaptive computing. o Mapping algorithms into hardware and synthesis of regular arrays.=20 o Parallelization and (space-time) partitioning of algorithms. o System architectures using configurable computing platform.=20 o Newly developed algorithms for efficient implementation on reconfigurable systems. 2. Software, CAD and Operating Systems. o CAD, specification, partitioning and verification. o Hardware compilation, hardware/software codesign, developing correct circuits. o High and low-level languages and compilers, design environments.=20 o Operating systems and run-time reconfiguring.=20 o IP-based and object oriented models and mapping methods.=20 3. Adaptive Hardware Architectures. o Adaptive and dynamically reconfigurable systems.=20 o Reconfigurable processor architectures. o Complex systems using reconfigurable processors. o Application-tailored reconfigurable Systems-on-Chip. o Low power systems on reconfigurable platform.=20 4. Applications. o Wireless communication systems --- mobile communication systems, video-phone, software radio,=20 global positioning systems etc. o Multimedia and virtual reality ---=20 video imaging, teleconferencing, data compression, image databases, computational geometry and computer graphics etc. o Automotive industry ---=20 vehicle guidance, lane and obstacle detection, object recognition, traffic systems, navigation of robots etc. o Security systems --- object recognition and tracking, cryptology, Internet and security etc.=20 o Classical image and signal processing --- digital filters, edge and line detection, morphological operators, motion and stereo estimation, discrete transformations, linear algebra, radar systems, object recognition etc. Preliminary List of Focus Sessions 1) High-level Synthesis of Reconfigurable Systems Chairman: Martin Middendorf, Univ. of Leipzig, Germany Email: middendorf@aifb.uni-karlsruhe.de o behavioural descriptions=20 o cost functions for reconfigurable systems=20 o optimization and design space exploration=20 o partitioning and scheduling=20 o resource allocation and binding=20 o control synthesis=20 o test, verification, and simulation approaches=20 o models for reconfigurable target architectures=20 =20 =20 2) Operating System for Reconfigurable Hardware Chairman: Marco Platzner, ETH, Zurich, Switzerland Email: platzner@tik.ee.ethz.ch o task and resource management =20 o scheduling: realtime and non-realtime =20 o interfaces and communication =20 o OS integration with host and networks =20 o design environments =20 o applications in embedded and general-purpose systems =20 =20 3) Java-based Environment for Reconfigurable Systems Chairman: Peter Athanas,Virginia Tech., USA =20 Email: athanas@vt.edu o Run-time reconfiguration o Design environments o Core libraries=20 o Synthesis and byte-code compilation o Applications 4) Configurable Computing Architectures and Hardware Chairman: Christian Siemers, Univ. of Applied Sciences Nordhausen,=20 Germany Email: siemers@fh-nordhausen.de o Space- and/or power-efficient architectures=20 o Architectures for runtime-definable space/time-mapping=20 o Architectural support for operating system and real-time=20 behavior =20 o Biology-inspired distributed architectures for configurable=20 computing =20 o Architecture definition and products for general and special=20 purpose application classes =20 =20 5) Configurable Systems-on-Chip=20 Chairman: Juergen Becker, Univ. of Karlsruhe, Germany=20 Email: becker@itiv.uni-karlsruhe.de o Application-tailored Configurable Datapath and Circuit=20 Structures =20 o Communication Interface Synthesis and SoC Integration =20 o IP-based Hardware/Software Co-Engineering and SoC Integration=20 Trade-offs =20 o Reconfigurable Instruction Set Integration for Processor-Cores =20 o Adaptivity, Self-Repairing and Testing Concepts for CSoCs =20 o CSoC Applications, Prototyping and Industrial Aspects =20 =20 6) Emerging Devices for Reconfigurable Systems Chairman: Steven Guccione, QuickSilver Tech., Inc., USA =20 Email: Steven.guccione@qstech.com 7) Low Power Systems Using FPGAs=20 Chairman: Ju-wook Jang, Sogang University, Korea =20 Email: jjang@sogang.ac.kr o Power/energy consumption modeling for FPGA devices=20 o Optimization techniques for Power/energy dissipation on FPGA=20 o Estimation of power consumption for designs on FPGA devices=20 o Low power/energy applications on FPGA=20 o Design methodology for low power/energy consumption for FPGA=20 o Low power implementation of network protocols using FPGA=20 o Low power implementation of multimedia processing using FPGA=20 o Other related issues=20 8) Reconfigurable Floating Point Processing Chairman: Maya Gokhale, Los Alamos National Laboratory, USA = =3D Email: maya@lanl.gov o customizable floating point libraries =20 o fixed point/floating point tradeoffs in area, clock frequency,=20 power =20 o experience with use of floating point on reconfigurable devices=20 for DSP, supercomputing or other applications =20 o experience with mixed mode fixed/floating point applications =20 o tools to infer optimal application-specific floating point sizes=20 for mantissa and exponent =20 o customized error handling in floating point arithmetic =20 o Reconfigurable cell architectures optimized for floating point =20 o Other floating point related topics : architectures, tools,=20 applications =20 =20 9) Software Defined Radio Chairman: Jeffrey Reed, Virginia Tech., USA =20 Email: reedjh@vt.edu =20 o Design methodologies for reconfigurable radios=20 o Custom Computing Machines (CCM) for Software Radios =20 o Flexible interconnects for high bandwidth I/O =20 o VLSI architectures for numerical communication algorithms in=20 Software radios eg: SVD, CORDIC =20 o Software communication architecture (SCA) implementation on CCMs =20 o Performance evaluation of radio architectures using DSPs FPGAs=20 and CCMs =20 o Issues with downloadable run time configuration=20 o Software/Hardware Verification =20 =20 =20 10) Custom Computing Machines for Image Processing Chairman: Marek Gorgon, TAGH University of Technology, Krakow,=20 Poland Email: mago@biocyb.ia.agh.edu.pl=20 o Reconfigurable Architectures for Image Processing =20 o Complex Image Processing Algorithms for CCM =20 o Real-time Imaging: Run Time Reconfiguration and Software/Hardware=20 Systems =20 o FPGA-based modules, libraries and IP Cores for Image Processing =20 o FPGA-based Image Compression=20 o Image co-processors and display accelerators=20 =20 11) will be extended.... For more details, visit our Web-site:=20 http://www.scism.sbu.ac.uk/ERA/ersa.html. =20 =20 If you have any questions or problems, please do not hesitate=20 to e-mail: ersa@sbu.ac.uk or directly to conference chair=20 Toomas Plaks: plakst@sbu.ac.uk (postal address is given below).=20 Conference Chairman Dr. Toomas P. Plaks email: plakst@sbu.ac.uk SCISM South Bank University 103 Borough Road London SE1 0AA United Kingdom General Co-Chair Prof. Peter M. Athanas=20 Virginia Tech., USA Industrial Co-Chair John Watson=20 QuickSilver Tech., Inc., USA =20 Advisory Board Prof. Reiner W. Hartenstein =20 Univ. of Kaiserslautern, Germany =20 Prof. Viktor K. Prasanna=20 Univ. of Southern California, USA =20 Dr. Nick Tredennick =20 Gilder Publishing, USA Steering Committee Carl Ebeling, University of Washington, USA=20 Hossam ElGindy, Univ. of New South Wales, Australia=20 Dominique Lavenier, IRISA, France Wayne Luk, Imperial College, UK =20 Lothar Thiele, ETH, Zurich, Switzerland=20 Programme Committee Peter Athanas, Virginia Tech., USA =20 Juergen Becker, Univ. of Karlsruhe, Germany =20 Oliver Diessel, Univ. of New South Wales, Australia =20 Carl Ebeling, Univ. of Washington, USA =20 Hossam ElGindy, Univ. of New South Wales, Australia =20 Maya Gokhale, Los Alamos National Laboratory, USA =20 Reiner Hartenstein, Univ. of Kaiserslautern, Germany=20 Ju-wook Jang, Sogang Univ., Korea =20 Jack Jean, Wright State Univ., USA =20 Lech Jozwiak, Eindhoven Univ. of Technology, The Netherlands =20 Richard Katz, NASA Goddard Space Flight Center, USA =20 Rainer Kress, Infineon Technologies, Germany =20 Dominique Lavenier, IRISA, France =20 Miriam Leeser, Northeastern Univ., USA =20 Bjorn Lisper, Univ. of Malardalen, Sweden =20 Wayne Luk, Imperial College, UK =20 John McHenry, National Security Agency, USA =20 Graham Megson, The Univ. of Reading, UK =20 Martin Middendorf, Univ. of Leipzig, Germany =20 Toomas Plaks, South Bank Univ., UK=20 Marco Platzner, ETH, Zurich, Switzerland =20 Bernard Pottier, Univ. of Bretagne Occidentale, France =20 Viktor Prasanna, Univ. of Southern California, USA=20 Sanjay Radopadhye, Colorado State Univ., USA =20 Jeffrey Reed, Virginia Tech., USA =20 Juergen Teich, Univ. of Paderborn, Germany =20 Lothar Thiele, ETH, Zurich, Switzerland =20 Nick Tredennick, Gilder Publishing, USA =20 Serge Vernalde, IMEC, Leuven, Belgium =20 John Watson, QuickSilver Tech., Inc., USA =20 Markus Weinhardt, PACT Informationstechologie GmbH, Germany =20 Michael Wirthlin, Brigham Young Univ., USA =20 -------------------------------------------------------------------------= - +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++ ASAP 2003 CALL FOR PAPERS +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++ 14th IEEE International Conference on Application-specific Systems, Architectures and Processors The Hague, The Netherlands, June 24-26, 2003 http://www.ece.rice.edu/asap2003/ Key dates: February 15, 2003: Deadline for submission of papers March 15, 2003: Acceptance notification April 6, 2003: Camera-ready papers due The conference will cover the theory and practice of application-specific systems, architectures and processors. Areas for application-specific com= puting are many and varied. Some sample areas include information systems, signa= l and image processing, multimedia systems, high-speed networks, compression, graphics, and cryptography.=20 Aspects of application-specific computing that are of interest include, b= ut are not limited to:=20 Application-specific systems: network computing, special-purpose systems, performance evaluation, design languages, compilers, operating systems, nanocomputing systems and applications, hardware/software integration, rapid-prototyping.=20 Application-specific architectures: special-purpose designs, design methodology, CAD tools, fault tolerance, specifications and interfaces, networks-on-a-chip, hardware/software codesign, processor arrays,=20 SoC, superscalar, multithreaded, VLIW, and EPIC architectures.=20 Application-specific processors: digital signal processing, computer arithmetic, configurable/custom computing, implementation methodologies, = new technologies, fine-grain parallelism, low-power designs, asynchronous har= dware.=20 The conference will feature a keynote speech, paper presentations, and recreational activities. The proceedings will be published by IEEE Comput= er Society Press. Conference Organizers ----------------------------=20 General Chairs:=20 Ed Deprettere, Leiden University Shuvra Bhattacharyya, University of Maryland =20 Program Chairs:=20 Lothar Thiele, Swiss Federal Institute of Technology Zuerich (Systems= ) Alain Darte, Ecole Normale Superieure de Lyon (Architectures) Joseph Cavallaro, Rice University (Processors)=20 Steering Committee: Jose Fortes, University of Florida=20 S-Y Kung, Princeton University Michael Schulte, University of Wisconsin Earl Swartzlander, University of Texas Program Committee: Shail Aditya, HP Labs Mark Arnold, Lehigh University Magdy Bayoumi, University of Louisiana at Lafayette Neil Burgess, Cardiff University Peter Cappello, University of California at Santa Barbara=20 Liang-Gee Chen, National Taiwan University Gerhard Fettweis, Dresden University of Technology Jose Fortes, University of Florida=20 Guang Gao, University of Delaware=20 Graham Jullien, University of Calgary Israel Koren, University of Massachusetts at Amherst S-Y Kung, Princeton University Tomas Lang, University of California at Irvine Ruby Lee, Princeton University Wayne Luk, Imperial College Elias Manolakos, Northeastern University=20 John McCanny, Queen's University of Belfast Jean-Michel Muller, Ecole Normale Sup. de Lyon Praveen Murthy, Fujitsu Laboratories of America=20 Tobias Noll, Aachen Institute of Technology Keshab Parhi, University of Minnesota at Twin Cities=20 Peter Pirsch, University of Hannover Gang Qu, University of Maryland Patrice Quinton, IRISA, Campus de Beaulieu Sanjay Rajopadhye, Colorado State University=20 Michael Schulte, University of Wisconsin-Madison Earl Swartzlander, University of Texas at Austin Juergen Teich, Paderborn University Mateo Valero, Technical University of Catalonia=20 Stamatis Vassiliadis, Delft University of Technology Ingrid Verbauwhede, University of California at Los Angeles Doran Wilde, Brigham Young University=20 Roger Woods, Queen's University of Belfast Kung Yao, University of California at Los Angeles Pen-Chung Yew, University of Minnesota at Twin Cities -------------------------------------------------------------------------= - =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D CALL FOR PAPERS ICS '03 17th International Conference on Supercomputing=20 June 23-26, 2003=20 San Francisco Bay Area=20 USA =20 Sponsored by ACM/SIGARCH =20 =20 ICS is the premier international forum for the presentation of research results in high-performance computing systems. Now in its 17th year, the conference also includes invited talks, tutorials, workshops, panels, and exhibits. The San Francisco Bay Area - the most sought after tourist destination in the entire world and the home of Silicon Valley - will host the conference in 2003. Papers are solicited on all aspects of research, development, and application of high-performance systems, including new experimental and commercial systems, architectures with fine and coarse grain parallelism, grid computing, novel infrastructures for the Internet, parallel I/O and storage, embedded and power-aware computer architectures, operating systems and support software, restructuring and optimizing compilers, program development tools, high-performance Java, performance evaluation studies, numerical or non-numerical algorithms, and computationally challenging scientific applications. Papers should not exceed 6,000 words, and must be submitted electronically using the submission form available at http://www.csit.fsu.edu/ics03. Submissions must be in PDF or postscript format. Workshop and tutorial proposals are solicited, and are due by March 17, 2003. For further information and future updates, refer to the ICS'03 web site at http://www.csit.fsu.edu/ics03, or contact the General or Program Chairs. GENERAL CHAIR Dr. Utpal Banerjee Intel Corporation Santa Clara, CA=20 utpal.banerjee@intel.com =20 PROGRAM CO-CHAIRS Prof. Kyle A. Gallivan=20 Florida State University=20 Tallahassee, FL=20 gallivan@csit.fsu.edu=20 Prof. Antonio Gonz=E1lez Intel Labs & Univ. Polit=E8cnica de Catalunya=20 Barcelona, Spain=20 antoniox.gonzalez@intel.com =20 IMPORTANT DATES Paper submission deadline: February 10, 2003 =20 Author notification: April 7, 2003=20 Final papers due: May 7, 2003 =20 =20 ------=20 ************************************************************************ * CALL FOR PAPERS * ************************************************************************ 2nd Annual Workshop on Novel Uses of System Area Networks (SAN-2) February 9, 2003 Held in conjunction with HPCA-9 The 9th International Symposium on High Performance Computer Architectur= e February 8-12, 2003 Anaheim, CA HOME PAGE http://www.csl.cornell.edu/SAN-2/ =20 OVERVIEW This one-day workshop will focus on innovative uses of emerging network technology for system area networks (SANs) and intelligent system area components (NICs, switches, disks, node controllers, etc.). As the price of individual cluster components continues to fall, and their performance steadily improves, clusters of PCs or workstations are becoming commonplace in areas once reserved for supercomputers or massively parallel architectures. The networks used in clusters have moved from traditional Ethernet to system area networks, such as the Virtual Interface Architecture, Myrinet, ServerNet, and the forthcoming InfiniBand and 3GIO (PCI Express) networks. System area networks are characterized by high bandwidth; low latency; a switched network environment; reliable transport service implemented directly in hardware; no kernel intervention to send and receive messages; and little or no copying on either the sending or receiving side. SANs may be used for enterprise applications such as databases, web servers, reservation systems, and parallel computing environments. The SAN-2 workshop will include presentations of accepted technical papers from both industry and academia and a keynote address by a speaker yet to be determined. =20 TOPICS This workshop will focus on non-traditional uses of commodity system area networks, intelligent SAN components, and innovative system area network architectures. Topics of interest include, but are not limited to, the following: =20 Intelligent system area components (NICs, switches, disks, node contro= llers, etc.)=20 SAN architecture enhancements=20 Clustering middleware that takes advantage of SAN hardware=20 Fault-tolerant SAN solutions=20 SAN-based shared memory architectures=20 Novel message-passing library implementations=20 Active I/O or Active Networking systems leveraging SAN architectures=20 Use of remote memory operations in SANs=20 Novel uses of SAN-based cluster architectures=20 Compilation support for SANs=20 Applications for clusters using SANs=20 =20 IMPORTANT DATES Submission Deadline: November 30, 2002 Notification to Authors: December 21, 2002 Final Papers Due: January 14, 2003 =20 SUBMISSIONS Authors should submit an extended abstract no longer than 5 pages for consideration. Reviews of all papers will be blind. Accepted papers must be no longer than 12 single-spaced pages (including figures, references, and appendices) using 12pt font. Submit one electronic copy of the abstract in PDF format via email to SAN2WORKSHOP@csl.cornell.edu by November 30. =20 Notification of acceptance will be given by December 21, and camera-ready papers will be due January 14. All accepted papers will be presented at the workshop and included in a bound proceedings that will be distributed at the workshop. Authors should use IEEE TOC format guidelines for final submissions. In addition, accepted papers will be made available on this site.=20 =20 PROGRAM COMMITTEE Ricardo Bianchini, Rutgers University Angelos Bilas, University of Toronto Mark Heinrich, Cornell University Pankaj Mehra, Hewlett Packard Li-Shiuan Peh, Princeton University Evan Speight, Cornell University Craig Stunkel, IBM Research -------------------------------------------------------------------------= - * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20